Systematic and automatic testing of electronic circuitry, and of integrated circuits in particular, has become increasingly more important. Each next generation of circuits tends to develop ever larger component densities and an ever growing number of system functionalities. Individual circuits have become complicated to such an extent that process defects cannot be detected and located anymore save by exhaustive and expensive testing. Customers cannot be expected to accept circuitry products that show their hidden defects in operational use, thereby rendering systems unreliable. It is therefore of the utmost importance for both the manufacturer and the customer that tests are run to guarantee flawless operation of the circuit products.
Quiescent-current testing (I.sub.DDQ -testing), also referred to as current supply monitoring method (CSM), of an integrated circuit aims at locating process defects in the circuit by monitoring the quiescent currents. For some details on I.sub.DDQ -testing, see "Design and Test Rules for CMOS Circuits to Facilitate I.sub.DDQ Testing of Bridging Faults", K.-J. Lee and M. A. Breuer, IEEE Transactions on Computer-Aided Design, Vol. II, No. 5, May 1992, pp. 659-669. The I.sub.DDQ -testing technique has shown a lot of promise in the analysis of actual process detects, typically in static CMOS ICs. The quiescent current, or steady state current, in a CMOS logic circuit should be very small, e.g., in the order of 1 .mu.A. Any deviation may therefore be easily detected. The potential of this testing technique is substantial in terms of cost reduction, and of quality and reliability enhancement.
Stuck-at faults are symptoms caused by unintended electrically conductive interconnections between circuit nodes and supply lines, thereby effecting a hard-wired pull-up or pull-down that interferes with the logic operation. A bridging fault formed by a conductive bridge of low resistance between a supply line and a signal line causes stuck-at phenomena. Impact of gate-oxide defects is often parametric in nature, i.e., not defined in terms of logic voltage levels, and is therefore often not detected by conventional voltage methods. Gate-oxide defects may also give rise to stuck-at behaviour.
It is an object of the invention to provide an I.sub.DDQ -testing method that more accurately diagnoses the measured quiescent current. It is another object to provide an I.sub.DDQ -testing method that discriminates between origins of quiescent currents.